1. Field of the Invention
The present invention relates to reference ladders, and more particularly, to interpolation of reference ladder voltages for use in programmable gain amplifiers (PGAs) and digital to analog converters (DACs).
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution). FIG. 1 shows the generic two-step subranging architecture, comprising a reference ladder 104, a coarse ADC 102, a switching matrix 103, a fine ADC 105, coarse comparators 107, fine comparators 108 and an encoder 106. In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102. The coarse ADC 102 compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage.
A flash ADC architecture is the most straightforward implementation of an analog-to-digital converter. Unfortunately, it is very inefficient in terms of area and power. In particular, an N-bit ADC requires 2N comparators. Furthermore, it requires a reference ladder with 2N taps, which generally causes a lot of wiring parasitic capacitance, slowing down the ADC.
A subranging ADC architecture is often used as a more power- and area-efficient alternative to the flash ADC architecture. While subranging does help to reduce the number of comparators, it does not help to reduce the number of taps on the reference ladder. In fact, the situation is complicated by the fact that subranging requires a switching matrix with a large number of switches. Parasitic capacitance associated with these switches slows down the ADC even further.
A conventional way of connecting the first row of amplifiers to the reference ladder is shown in FIG. 2: amplifier A1 connects to reference taps “2m” and “0”, amplifier A2 connects to a “2m−1 ” tap and a “1” tap, etc. Thus, in a “brute force” flash ADC, the reference ladder 104 has 2N=2m taps (e.g., 1024 taps for N=10).
Three techniques have been published in the literature for decreasing the number of switches in subranging ADC's. First, interpolation between preamplifier output voltages is often used. Interpolation is often applied in both flash ADC's, subranging ADC's and folding ADC's. This form of interpolation reduces the number of amplifiers in a first array of amplifiers. Since only the first array of amplifiers needs connections to the reference ladder 104, this technique reduces the required number of reference taps and switches. For example, 4× interpolation within the fine ADC 105 reduces the number of switches by 75%.
A second technique for reducing the number of switches is referred to as “absolute value processing.” See B. P. Brandt and J. Lutsky. “A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist,” IEEE Jour. of Solid State Circ., 34(12):1788-1795 (December 1999). This technique uses the fact that the absolute value function can be implemented simply by a commutator, basically comprising only four switches. This technique reduces the required number of switches in the matrix 103 by another 50%. Note that this technique does not reduce the number of taps on the reference ladder 104.
A third technique called “multilevel tree decoding scheme” decreases the number of switches by 62.5%. (See, e.g., Ito et al., “A 10-bit 20 MS/s 3V Supply CMOS A/D converter,” IEEE J. of Solid State Circ., 29 (12):1532-36, December 1994) Note that this technique does not reduce the number of taps on the reference ladder 104.
For example, a 10-bit analog digital converter in a “brute force” flash type configuration would require 210, or 1024 taps on the reference ladder, which is very awkward. Thus, the problem involves the total number of taps required from the reference ladder, as well as the number of switches in the switch matrix for a subranging analog digital converter. It is therefore desirable to reduce the number of taps, which reduces the amount of parasitic capacitance due to the connections involved.
Accordingly, a need exists for an ADC circuit topology that significantly reduces the number of switches and taps from the reference ladder 104.